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| TM HM-6516/883 2K x 8 CMOS RAM Description The HM-6516/883 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also gives fast access times. The pinout of the HM6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard which allows easy memory board layouts, flexible enough to accommodate a variety of PROMs, RAMS, EPROMs, and ROMs. The HM-6516/883 is ideally suited for use in microprocessor based systems. The byte wide organization simplifies the memory array design, and keeps operating power down to a minimum because only one device is enabled at a time. The address latches allow very simple interfacing to recent generation microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable. March 1997 Features * This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby. . . . . . . . . . . . . . . . . . . 275W Max * Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max * Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max * Industry Standard Pinout * Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC * TTL Compatible * Static Memory Cells * High Output Drive * On-Chip Address Latches * Easy Microprocessor Interfacing Ordering Information 120ns HM1-6516B/883 HM4-6516B/883 200ns HM1-6516/883 TEMPERATURE RANGE PACKAGE -55oC to 125oC -55oC to +125oC CERDIP CLCC PKG. NO. F24.6 J32.A Pinouts HM-6516/883 (CERDIP) TOP VIEW NC A7 HM-6516/883 (CLCC) TOP VIEW VCC NC NC NC NC PIN NC 29 A8 28 A9 27 NC 26 W 25 G 24 A10 23 E 22 DQ7 21 DQ6 DESCRIPTION No Connect Address Inputs Chip Enable/Power Down Ground A7 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 DQ0 9 DQ1 10 DQ2 11 GND 12 24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 DQ0 13 3 2 1 32 31 30 A0 - A10 E VSS/GND DQ0 - DQ7 Data In/Data Out VCC W G Power (+5V) Write Enable Output Enable 14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 GND DQ5 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved FN2999.1 173 HM-6516/883 Functional Diagram A 7 LATCHED ADDRESS REGISTER GATED ROW DECODER 128 128 x 128 MATRIX 1 OF 8 G G G W E L 16 16 16 16 16 16 16 16 GATED COLUMN DECODER 4 4 A 8 A A A LATCHED ADDRESS REGISTER A3 A2 A1 A0 8 DQ0 THRU DQ7 A10 A9 A8 A7 A6 A5 A4 A 7 L 174 HM-6516/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades. . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W oC to +150oC Maximum Storage Temperature Range . . . . . . . . .-65 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max TABLE 1. HM-6516/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Operating Supply Current Standby Supply Current SYMBOL VOH (NOTE 1) CONDITIONS VCC = 4.5V IO = -1.0mA VCC = 4.5V IO = 3.2mA VCC = G = 5.5 V, VIO = GND or VCC GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.4 MAX UNITS V VOL 1, 2, 3 - 0.4 V A IIOZ 1, 2, 3 -1.0 1.0 II VCC = 5.5V, VI = GND or VCC VCC = G = 5.5V, (Note 2) f = 1MHz, VI = GND or VCC VCC = 5.5V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC VCC = 5.5V, HM-6516B/883 E = VCC -0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -1.0 1.0 A ICCOP 1, 2, 3 - 10 mA A ICCSB1 1, 2, 3 - 100 1, 2, 3 -55oC TA +125oC - 50 A Data Retention Supply Current ICCDR VCC = 2.0V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC VCC = 2.0V, HM-6516B/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC TA +125oC - 50 A 1, 2, 3 -55oC TA +125oC - 25 A Functional Test NOTES: FT VCC = 4.5V (Note 3) 7, 8A, 8B -55oC TA +125oC - - - 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V. 175 HM-6516/883 TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) PARAMETER Chip Enable Access Time Address Access Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Set-up Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Set-up Time Chip Selection to End of Write Data Set-up Time Data Hold Time Read or Write Cycle Time SYMBOL CONDITIONS VCC = 4.5 and 5.5V GROUP A SUBGROUPS 9, 10, 11 HM-6516B/883 TEMPERATURE -55oC T A +125oC -55oC T A +125oC -55oC T A +125oC MIN MAX 120 HM-6516/883 MIN MAX 200 UNITS ns (1) TELQV (2) TAVQV (9) TELEH VCC = 4.5 and 5.5V, (Note 3) VCC = 4.5 and 5.5V 9, 10, 11 - 120 - 200 ns 9, 10, 11 120 - 200 - ns (10) TEHEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC T A +125oC 50 - 80 - ns (11) TAVEL (12) TELAX (13) TWLWH (14) TWLEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC T A +125oC -55oC T A +125oC -55oC T A +125oC -55oC T A +125oC 0 - 0 - ns VCC = 4.5 and 5.5V 9, 10, 11 30 - 50 - ns VCC = 4.5 and 5.5V 9, 10, 11 120 - 200 - ns VCC = 4.5 and 5.5V 9, 10, 11 120 - 200 - ns (15) TELWH (16) TDVWH (17) TWHDX (18) TELEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC T A +125oC -55oC T A +125oC -55oC T A +125oC -55oC T A +125oC 120 - 200 - ns VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V 9, 10, 11 9, 10, 11 9, 10, 11 50 10 170 - 80 10 280 - ns ns ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 176 HM-6516/883 TABLE 3. HM-6516/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER Input Capacitance SYMBOL CI CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground Input/Output Capacitance CIO VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground Chip Enable to Output Valid Time Write Enable Output Disable Time NOTES 1, 2 TEMPERATURE TA = +25oC MIN - MAX 8 UNITS pF 1, 3 TA = +25oC - 12 pF 1, 2 TA = +25oC - 10 pF 1, 3 TA = +25oC - 14 pF (3) TELQX (4) TWLQZ VCC = 4.5 and 5.5V 1 -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC -55oC TA +125 oC 10 - ns VCC = 4.5 and 5.5V HM-6516/883 VCC = 4.5 and 5.5V HM-6516B/883 1 - 80 ns 1 - 50 ns Chip Enable Output Disable Time (5) TEHQZ VCC = 4.5 and 5.5V HM-6516/883 VCC = 4.5 and 5.5V HM-6516B/883 1 - 80 ns 1 - 50 ns Output Enable Access Time (6) TGLQV (7) TGLQX (8) TGHQZ VCC = 4.5 and 5.5V 1 - 80 ns Output Enable to Output Valid Time Output Disable Time VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V HM-6516/883 VCC = 4.5 and 5.5V HM-6516B/883 1 10 - 80 ns ns 1 1 - 50 ns NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to LCC device types only. 3. Applies to DIP device types only. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 177 HM-6516/883 Timing Waveforms (2) TAVQV (12) TELAX (11) A TAVEL VALID ADD (18) TELEL (10) TEHEL E HIGH W (5) TEHQZ (1) TELQV (5) TELQX DQ (6) TGLQV G (7) TGLQX TIME REFERENCE -1 0 1 2 3 4 5 VALID DATA OUT TGHQZ (8) (5) TEHQZ (9) TELEH (10) TEHEL (11) TAVEL NEXT ADD FIGURE 1. READ CYCLE The address information is latched in the on-chip registers on the falling edge of E (T = 0), minimum address setup and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1), the outputs become enabled but data is not valid until time (T = 2), W must remain high throughout (11) TAVEL A (12) TELAX the read cycle. After the data has been read, E may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). G is used to disable the output buffers when in a logical "1" state (T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for the next cycle. (11) TAVEL NEXT ADD (18) TELEL VALID ADD (10) TEHEL E (9) TELEH (10) TEHEL (14) TWLEH (13) TWLWH W (15) TELWH (16) TDVWH VALID DATA IN (17) TWHDX DQ G TIME REFERENCE -1 0 1 HIGH 2 3 4 5 FIGURE 2. WRITE CYCLE The write cycle is initiated on the falling edge of E (T = 0), which latches the address information in the on-chip registers. If a write cycle is to be performed where the output is not to become active, G can be held high (inactive). TDVWH and TWHDX must be met for proper device operation regardless of G. If E and G fall before W falls (read mode), a possible bus conflict may exist. If E rises before W rises, reference data setup and hold times to the E rising edge. The write operation is terminated by the first rising edge of W (T = 2) or E (T = 3). After the minimum E high time (TEHEL), the next cycle may begin. If a series of consecutive write cycles are to be performed, the W line may be held low until all desired locations have been written. In this case, data setup and hold times must be referenced to the rising of E. 178 HM-6516/883 Test Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuits HM-6516/883 CERDIP TOP VIEW F10 HM-6516/883 CLCC TOP VIEW VCC VCC C NC NC NC NC A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 NC A7 F10 F9 F8 F7 F6 F5 F4 F3 F2 F2 F2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A7 VCC F11 F12 F1 F0 F13 F0 F4 F2 F2 F2 F2 F2 F2 F3 F9 F8 F7 F6 F5 A6 A5 A4 A3 A2 A1 A0 5 6 7 8 9 10 11 4 3 2 1 C 32 31 30 29 28 A8 A9 F11 F12 NC 12 DQ0 13 14 15 16 17 18 DQ1 DQ2 NC DQ3 GND 19 20 DQ4 DQ5 27 NC W 26 G 25 A10 24 E 23 DQ7 22 DQ6 21 F1 F0 F13 F0 F2 F2 F2 F2 F2 F2 NOTES: All resistors 47k 5%. F0 = 100kHz 10%. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C1 = 0.01F Min. 179 F2 HM-6516/883 Die Characteristics DIE DIMENSIONS: 186.6 x 199.6 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 9kA - 13kA GLASSIVATION: Type: SiO2 Thickness: 7kA 9kA WORST CASE CURRENT DENSITY: 0.5 x 105 A/cm 2 Metallization Mask Layout HM-6516/883 A3 A4 A2 A5 A6 A7 VCC A8 A9 W G A10 A1 E A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 180 |
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